1. Field of the Invention
The present invention relates to the erase mode in a flash memory array. More particularly, the present invention relates to a page erase mode and multiple page erase mode in a flash memory array.
2. The Prior Art
In a conventional flash memory array, the flash memory array is typically arranged as a matrix of wordlines and bitlines to form intersections with flash memory elements disposed at the intersections in a manner well known to those of ordinary skill in the art. The operations that may be performed on the memory cells in the flash memory array are READ, PROGRAM and ERASE.
The PROGRAM operation is often performed by driving selected bitlines connected to the drain region in the flash memory cells to a first voltage and driving the gates of the flash memory cells connected to selected wordlines to a higher voltage to perform hot electron injection in a manner well known to those of ordinary skill in the art.
The ERASE operation is performed by driving the gate of the flash memory cell to a voltage that is substantially less than a voltage placed on the bitline. In doing so, electrons are tunneled off of the floating gate of the flash memory cells in a manner well known to those of ordinary skill in the art. For conventional flash memory arrays, it is known that either the entire flash memory array may be erased at one time, known as BULK ERASE, or that a sector in the flash memory array may be erased at one time, known as SECTOR ERASE. An example of a BULK ERASE of a flash memory array is found in the paper xe2x80x9cA 90 ns 100K Erase-Program Cycle Megabit Flash Memoryxe2x80x9d, 1989, IEEE International Solid State Circuits Conference, pages 140 and 141, February 1989. An example of a SECTOR ERASE is found in the paper entitled, xe2x80x9cA 55 ns 0.35 xcexcm 5V Only 16M Flash Memory with Deep-Power-Downxe2x80x9d, 1996, IEEE International Solid-State Circuits Conference, pages 44 and 45, February 1996.
Constraining the ERASE operation to either a SECTOR or BULK ERASE is done in consideration of the fact that when individual row lines are selected to be erased, there is the possibility the value stored on the floating gate of flash memory cells for unselected rows will be affected due to the occurrence of unintended tunneling. Accordingly, it is an object of the present invention to provide an erase mode wherein only a single row in a sector or multiple rows in a sector may be erased while reducing the disturb phenomenon for flash memory cells in the sector that are not selected.
According to the first aspect of the present invention, a PAGE ERASE mode of operation is provided for a sector in a flash memory array. In the PAGE ERASE mode of operation, a preferred tunneling potential of approximately xe2x88x9210 Volts is applied to the gates of the flash memory cells on the row being selected for PAGE ERASE, and the bitlines connected to the drains of the flash memory cells are driven to a preferred voltage of approximately 6.5 Volts. To reduce the unintended erasure of memory cells in rows other than the selected row, a preferred bias voltage of approximately 1 to 2 Volts is applied to the gates of all the flash memory cells in the rows other than the selected row.
According to a second aspect of the present invention, a MULTIPLE PAGE ERASE mode is provided. In the MULTIPLE PAGE ERASE mode, the rows in a sector are partitioned into groups, and more than one row in the group is selected to be erased or corresponding rows in different groups are selected to be erased. In MULTIPLE PAGE ERASE mode a preferred tunneling voltage of approximately xe2x88x9210 Volts to the gates of the flash memory cells in the rows selected for erasure, and the bitlines connected to the drains of the flash memory cells are driven to a preferred voltage of approximately 6.5 Volts. To reduce the occurrence of unintended erasure of flash memory cells on rows that are not selected, a preferred bias voltage of approximately 1 to 2 Volts is applied to the gates of the flash memory cells in rows that have not been selected for erasure.